View HFA3761_179264.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HFA3761
TM
Data Sheet
July 1999
File Number
4236.4
400MHz AGC and Quadrature IF Demodulator
The HFA3761 is a highly integrated baseband converter for quadrature demodulation applications. The HFA3761 400MHz AGC and quadrature IF demodulator is one of the seven chips in the PRISM(R) full duplex chip set (see Typical Application Diagram). It features all the necessary blocks for baseband demodulation of I and Q signals. It has a two stage integrated AGC IF amplifier with 82dB of voltage gain and 76dB of gain control range. Baseband antialiasing and shaping filters are integrated in the design. Four filter bandwidths are programmable via a two bit digital control interface. In addition, these filters are continuously tunable over a 20% frequency range via one external resistor. To achieve broadband operation, the Local Oscillator frequency input is required to be twice the desired frequency of demodulation. A selectable buffered divide by 2 LO output and a stable reference voltage are provided for convenience of the user. The device is housed in a thin 80 lead TQFP package well suited for PCMCIA board applications.
Features
* Integrates all IF and AGC Receive Functions * Broad Frequency Range . . . . . . . . . . 10MHz to 400MHz * I/Q Amplitude and Phase Balance . . . . 0.2dB, 2 Degrees * 5th Order Programmable Low Pass Filter . . . . . . . . . . . . . . . . . 2.2MHz to 17.6MHz * 400MHz AGC Gain Strip . . . . . . . . . . . . . . . . . . . . . 82dB * AGC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75dB * Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm * Fast AGC Switching . . . . . . . . . . . . . . . . . . . . . . . . . . 1s * Power Management/Standby Mode * Single Supply 2.7V to 5.5V Operation
Applications
* Wireless Local Loop * Wireless Local Area Networks * PCMCIA Wireless Transceivers * ISM Systems * CDMA Radios * PCS/Wireless PBX
Ordering Information
PART NUMBER HFA3761IN TEMP. RANGE (oC) -40 to 85 PACKAGE 80 Ld TQFP PKG. NO. Q80.14x14
Simplified Block Diagram
DEMOD_RX_I DEMOD_RX_Q DEMOD_IF_IN LPF_TUNE_1 LPF_TUNE_0 AGC1_OUT AGC2_OUT LPF_RX_Q LPF_RX_I AGC2_IN
AGC_SEL AGC1_IN AGC1_VAGC AGC2_VAGC DEMOD_LO_IN DEMOD_LO_OUT LO_GND I
LPF_RXI_OUT
LPF_RXQ _OUT Q
/2
0o/90o
2V REF LPF_SEL0 LPF_SEL1 2V REF
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 PRISM(R) is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
HFA3761 Pinout
80 LEAD TQFP TOP VIEW
AGC1_VAGC GND AGC1_VCC AGC1_PE AGC1_OUT+ AGC1_OUTAGC1_VCC GND GND GND GND GND GND GND GND AGC2_BYPAGC2_INGND AGC2_IN+ AGC2_BYP+ 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AGC1_BYP+ AGC1_IN+ GND AGC_SEL AGC1_INAGC1_BYPGND GND LPF_VCC 2V REF LPF_BYP NC NC LPF_RXI_OUT LPF_RXQ_OUT LPF_SEL1 LPF_SEL0 LPF_TUNE1 LPF_TUNE0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 LPF_RX_PE GND NC NC NC NC LPF_RXQLPF_RXQ+ LPF_RXILPF_RXI+ GND GND DEMOD_RXI+ DEMOD_RXIDEMOD_RXQ+ DEMOD_RXQNC NC NC NC 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AGC2_VAGC GND AGC2_VCC AGC2_PE AGC2_OUT+ AGC2_OUTAGC2_VCC GND GND GND LO_GND DEMOD_IFINDEMOD_IFIN+ DEMOD_VCC LO_OUT DEMOD_VCC LO_IN DEMOD_RX_PE DEMOD_VCC GND
Typical Full Duplex Application Diagram
PRISM FULL DUPLEX CHIP SET
HFA3424/21 (File #4131) D U P L E X E R LNA BPF HFA3661 (File #4240) LNA RF/IF CONVERTER RF LO1 HFA3524 (File #4062) SYNTHESIZER IF LO1 BASEBAND HFA3524 (File #4062) HFA3925 (File #4132) PA BPF SYNTHESIZER RF LO2 AGC IF/RF CONVERTER HFA3663 (File #4241) HFA3664 (File #4242) AGC QMODEM LPF OPTIONAL WHEN IN ANALOG MODE PRISM FULL DUPLEX RADIO CHIP SET, FILE #4238 IF LO2 HFA3763 (File #4237) LPF D/A HFA3761 (File #4236) FILTER IF AGC QMODEM LPF LPF A/D
For additional information on the PRISM Full Duplex Radio Chip Set, call (321) 724-7800 to access Intersil' AnswerFAX system. When prompted, key in the four-digit document number (File #) of the data sheets you wish to receive. 4-2
The four-digit file numbers are shown in Typical Application Diagram, and correspond to the appropriate circuit.
HFA3761 Block Diagram
LPF_TUNE0 LPF_TUNE1 LPF_RX PE LPF_RX I LPF_RX I + LPF_RX Q + LPF_RX Q DEMOD_RX Q DEMOD_RX Q + DEMOD_RX I DEMOD_RX I + DOWN CONV
LPF_RXI_OUT
LPF_RXQ_OUT
LPF_SEL1 LPF_SEL0
DEMOD_RX PE
0o / 90o
2V REF
AGC2_OUT AGC2_OUT + AGC2_PE AGC1_PE AGC2_IN+ AGC2_INAGC1_OUT AGC1_OUT +
AGC_SEL
AGC1_IN+
AGC1_IN-
SAW
AGC1_VAGC
AGC2_VAGC
LO_GND DEMOD_LO_OUT DEMOD_LO_IN (2XLO)
OPTIONAL FILTER
IF
IF
AGC CTRL
/2
DEMOD_IF_IN + DEMOD_IF_IN -
NOTE: VCC , GND and Bypass capacitors not shown.
4-3
IF IN
50
HFA3761 Pin Descriptions
PIN 1 2 3 4 5, 6, 7, 8 9 10 11 12 13 14 15 16 17 SYMBOL AGC1_BYP+ AGC1_In+ GND AGC_Sel AGC1_InAGC1_BYPGND LPF_VCC 2V REF LPF_BYP NC NC LPF_RXI_Out LPF_RXQ_Out LPF_Sel1 LPF_Sel0 DESCRIPTION DC feedback pin for AGC amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground. Non-inverting analog input of AGC amplifier 1. Ground. Connect to a solid ground plane. This pin selects either differential or single ended input configuration for the first stage AGC. Ground this pin for differential input configuration. Leave it floating for single ended input configuration. Inverting analog input of AGC amplifier 1. DC feedback pin for AGC amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground. Ground. Connect to a solid ground plane. Supply pin for the Low pass filter. Use high quality decoupling capacitors right at the pin. Stable 2V reference voltage output for external applications. Loading must be higher than 10k. A bypass capacitor of at least 0.1F is required. Internal reference bypass pin. This is the common voltage (VCM) used for the LPF digital thresholds. Requires 0.1F decoupling capacitor. Connected internally for test purposes. Pin must be left floating. Connected internally for test purposes. Pin must be left floating. Low pass filter in phase (I) channel receive output. Requires AC coupling. Low pass filter quadrature (Q) channel receive output. Requires AC coupling. Digital control input pins. Selects four programed cut off frequencies for the receive channel. Tuning speed from one cutoff to another is less than 1s. SEL1 LO LO 18 19 20 21 22 23 24 25 26 27 28 29 30 31, 32 33 34 LPF_Tune1 LPF_Tune0 GND LPF_RX_PE GND NC NC NC NC LPF_RXQLPF_RXQ+ LPF_RXILPF_RXI+ GND DEMOD_RXI+ DEMOD_RXISEL0 LO HI CUTOFF FREQUENCY 2.2MHz 4.4MHz SEL1 HI HI SEL0 LO HI CUTOFF FREQUENCY 8.8MHz 17.6MHz
These two pins are used to fine tune the Low pass filter cutoff frequency. A resistor connected between the two pins (RTUNE) will fine tune both transmit and receive filters. Refer to the tuning equation in the LPF AC specifications. Ground. Connect to a solid ground plane. Digital input control pin to enable the LPF receive mode of operation. Enable logic level is High. Ground. Connect to a solid ground plane. Connected internally for test purposes. Pin must be left floating. Connected internally for test purposes. Pin must be left floating. Connected internally for test purposes. Pin must be left floating. Connected internally for test purposes. Pin must be left floating. Low pass filter inverting input of the receive quadrature channel. AC coupling is required. This input is normally coupled to the negative output of the quadrature demodulator (Mod_RXQ-), pin 36. Low pass filter non inverting input of the receive quadrature channel. AC coupling is required. This input is normally coupled to the positive output of the quadrature demodulator (Mod_RXQ+), pin 35. Low pass filter inverting input of the receive in phase channel. AC coupling is required. This input is normally coupled to the negative output of the in phase demodulator (Mod_RXI-), pin 34. Low pass filter non inverting input of the receive in phase channel. AC coupling is required. This input is normally coupled to the positive output of the in phase demodulator (DEMOD_RXI-), pin 33. Ground. Connect to a solid ground plane. In phase demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the Low pass filter (LPF_RXI+), pin 30. In phase demodulator negative output. AC coupling is required. Normally connects to the inverting input of the Low pass filter (LPF_RXI-), pin 29.
4-4
HFA3761 Pin Descriptions
PIN 35 36 37 38 39 40 41 42 43 44 SYMBOL (Continued) DESCRIPTION
DEMOD_RXQ+ Quadrature demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the Low pass filter (LPF_RXQ+), pin 28. DEMOD_RXQNC NC NC NC GND DEMOD_VCC DEM_RX_PE DEM_LO_In (2XLO) Quadrature demodulator negative output. AC coupling is required. Normally connects to the inverting input of the Low pass filter (LPF_RXQ+), pin 27. Connected internally for test purposes. Pin must be left floating. Connected internally for test purposes. Pin must be left floating. Connected internally for test purposes. Pin must be left floating. Connected internally for test purposes. Pin must be left floating. Ground. Connect to a solid ground plane. Supply pin for the Demodulator. Use high quality decoupling capacitors right at the pin. Digital input control to enable the demodulator section. Enable logic level is High. Single ended local oscillator current input. Frequency of input signal must be twice the required demodulator LO frequency. Input current is optimum at 200ARMS. Input matching networks and filters can be designed for a wide range of power and impedances at this port. Typical input impedance is 130. This pin requires AC coupling. NOTE: High second harmonic content input waveforms may degrade I/Q phase accuracy. Supply pin for the Demodulator. Use high quality decoupling capacitors right at the pin. Divide by 2 buffered output reference from "DEMOD_LO_in" input. Used for external applications where the demodulating carrier reference frequency is required. 50 single end driving capability. This output can be disabled by use of pin 50. AC coupling is required. Supply pin for the Demodulator. Use high quality decoupling capacitors right at the pin. Demodulator, non-inverting input. Requires AC coupling. Demodulator, inverting input. Requires AC coupling. When grounded, this pin enables the LO buffer (DEMOD_LO_Out). When open (NC) it disables the LO buffer. Ground. Connect to a solid ground plane. Supply pin for the AGC amplifier 2. Use high quality decoupling capacitors right at the pin. Positive output of AGC amplifier 2. Requires AC coupling. Negative output of AGC amplifier 2. Requires AC coupling. Digital input control to enable the AGC amplifier 2. Enable logic level is High. Supply pin for the AGC amplifier 2. Use high quality decoupling capacitors right at the pin. Ground. Connect to a solid ground plane. AGC amplifier 2, AGC control input. DC feedback pin for AGC amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground. Non-inverting analog input of AGC amplifier 2. Ground. Connect to a solid ground plane. Inverting input of AGC amplifier 2. DC feedback pin for AGC amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground. Ground. Connect to a solid ground plane. AGC amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin. Negative output of AGC amplifier 1. Requires AC coupling. Positive output of AGC amplifier 1. Requires AC coupling. Digital input control to enable the AGC amplifier 1. Enable logic level is High. AGC amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin. Ground. Connect to a solid ground plane. AGC amplifier 1, AGC control input.
45 46
DEMOD_VCC DEM_LO_Out
47 48 49 50 51, 52, 53 54 55 56 57 58 59 60 61 62 63 64 65 66 - 73 74 75 76 77 78 79 80
DEMOD_VCC DEMOD_IFIN+ DEMOD_IFINLO_GND GND AGC2_VCC AGC2_OutAGC2_Out+ AGC2_PE AGC2_VCC GND AGC2_VAGC AGC2_BYP+ AGC2_In+ GND AGC2_InAGC2_BYPGND AGC1_VCC AGC1_OutAGC1_Out+ AGC1_PE AGC1_VCC GND AGC1_VAGC
4-5
HFA3761
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Package Power Dissipation at 70oC TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.1W Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . -65oC TA 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (TQFP - Lead Tips Only)
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 to 5.5V Operating Temperature Range . . . . . . . . . . . . . . -40oC TA 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Cascaded DC Electrical Specifications
VCC = 4.5V to 5.5V, Unless Otherwise Specified (NOTE 2) TEST LEVEL A A A A A A A A A A A A A A A C A B B B A B B C
PARAMETER Total Supply Current, at 5.5V Shutdown (Standby) Current at 5.5V All Digital Inputs VIH (TTL Threshold for All VCC) All Digital Inputs VIL (TTL Threshold for All VCC) High Level Input Current at 5.5V VCC for pins 16 and 21 with VIN = 2.4V High Level Input Current at 5.5V VCC for pins 16 and 21 with VIN = 4.0V Low Level Input Current at 5.5V VCC for pins 16 and 21 with VIN = 0.8V High Level Input Current at 5.5V VCC for pin 17, with VIN = 2.4V High Level Input Current at 5.5V VCC for pin 17, with VIN = 4.0V Low Level Input Current at 5.5V VCC for pin 17, with VIN = 0.8V High Level Input Current at 5.5V VCC for pin 43 with VIN = 2.4V High Level Input Current at 5.5V VCC for pin 43 with VIN = 4.0V Low Level Input Current at 5.5V VCC for pin 43 with VIN = 0.8V VAGC Input for Max Gain (Note 5) VAGC Input for Min Gain (Note 5) VAGC Control Input Impedance (Per Stage) (Note 3) VAGC Control Input Current (Per Stage) at Max Control Voltage Full Range AGC Switching Large Signal Recovery (Note 4) Full Range AGC Switching 1dB Settling Time (Note 4) Power Down/Up Switching Speed (Note 4) Reference Voltage Reference Voltage Variation Over Temperature Reference Voltage Variation Over Supply Voltage Reference Voltage Minimum Load Resistance NOTES: 2. A = Production Tested, B = Based on Characterization, C = By Design. 3. 1.2V reference source in series with 410. 4. Determined by external components. 5. Measured at probe.
TEMP (oC) Full Full Full Full Full Full Full Full Full Full Full Full Full 25 25 25 25 25 25 25 Full 25 25 25
MIN 2.0 -0.2 -200 -150 -300 0 0 0 -20 0 -20 .8 1.85 10
TYP 80 .8 -65 -30 -95 50 80 15 1 110 .1 1.1 2.1 410 .5 400 1.5 2 2.0 800 1.6 -
MAX 112 1.5 VCC 0.8 0 0 0 200 300 150 20 300 20 2.2 2.0 2.15 -
UNITS mA mA V V A A A A A A A A A V V mA ns s s V V/oC mV/V k
4-6
HFA3761
Cascaded AC Electrical Specifications, Demodulator Chain Performance
MHz, Unless Otherwise Specified (NOTE 6) TEST LEVEL A C A A TBD VCC = 4.5v to 5.5v, LO = 560 MHz, and IF=280
PARAMETER IF Demodulator I and Q Outputs Voltage Swing (IF input Range of -70 dBm to -30 dBm) IF Demodulator I and Q Channels Output Drive Capability (ZOUT = 50) CMAX = 10pF, VOUT = 500mVP-P IF Demodulator I/Q Amplitude Balance, IFin = -70dBm at 50 IF Demodulator I/Q Phase Balance, IFin = -70dBm at 50 IF Demodulator Output, P1dB NOTES:
TEMP. (oC) Full 25 Full Full TBD
MIN 250 1.2 -1.0 -4.0 TBD
TYP 2 0 0 TBD
MAX +1.0 +4.0 TBD
UNITS mVP-P k dB Degrees mV
6. A = Production Tested, B = Based on Characterization, C = By Design. 7. Determined by external components.
AC Electrical Specifications, Cascaded AGC Stages Performance
(NOTE 8) TEST LEVEL B A B B B B B B B B B B
VCC = 4.5V to 5.5V
PARAMETER Frequency Range (Note 9) Voltage Gain at Max Gain (Note 10) (VAGC = 0.8V, RS = 50, RL = 500) Voltage Gain at Min Gain (VAGC = 2.1V, RS = 50, RL = 500) Noise Figure at Max Gain, RS = 50 Output P 1dB at Min Gain, RS = 50, dBm into RL = 500 Input P 1dB at Min Gain, RS = 50 Output IP3 at Min Gain, dBm into RL = 500 Input IP3 at Min Gain, RS = 50 Group Delay, 20MHz Bandwidth Single Ended Input Impedance, AGC_SEL = floating Differential Input Impedance, AGC_SEL = ground Differential Output Impedance NOTES:
TEMP. (oC) 25 25 25 25 25 25 25 25 25 25 25 25
MIN 10 78 -16 -13 -5 -2 -
TYP 82 7 10 -13 -10 -2 1 2.0 50 100 80
MAX 400 11 -
UNITS MHz dB dB dB dBm dBm dBm dBm nsP-P
8. A = Production Tested, B = Based on Characterization, C = By Design. 9. Determined by external components. 10. Measured at probe.
AC Electrical Specifications, I/Q Down Converter Individual Performance
(NOTE 11) TEST LEVEL B C B C C
VCC = 4.5V to 5.5V
PARAMETER Quadrature Demodulator Input Frequency Range Demodulator Baseband I/Q Frequency Range Demodulator Voltage Gain Over Frequency Range Demodulator Differential Input Resistance Demodulator Differential Input Capacitance
TEMP. (oC) 25 25 25 25 25
MIN 10 6 -
TYP 8 1 0.5
MAX 400 30 9 -
UNITS MHz MHz dB k pF
4-7
HFA3761
AC Electrical Specifications, I/Q Down Converter Individual Performance
(NOTE 11) TEST LEVEL B A A B B VCC = 4.5V to 5.5V (Continued)
PARAMETER Demodulator Differential Output Level at 4K Load, (Output Controlled By AGC Action) Demodulator Amplitude Balance Demodulator Phase Balance at 286MHz Demodulator Phase Balance at 400MHz Demodulator Output 1dB Compression Voltage at 4K Load NOTE:
TEMP. (oC) 25 25 25 25 25
MIN 400 -1.0 -4 -4 -
TYP 500 1.25
MAX 560 1.0 4 4 -
UNITS mVP-P dB Degrees Degrees VP-P
11. A = Production Tested, B = Based on Characterization, C = By Design.
AC Electrical Specifications, LO Individual Performance
VCC = 4.5V to 5.5V
PARAMETER 2XLO Input Frequency Range (2 X Input Range) 2XLO Input Current Range 2XLO Input Impedance Buffered LO Output Voltage, Single Ended Buffered LO Output Impedance NOTE:
(NOTE 12) TEST LEVEL B C C C C
TEMP. (oC) 25 25 25 25 25
MIN 20 50 50 -
TYP 200 130 100 50
MAX 800 300 -
UNITS MHz ARMS mVP-P
12. A = Production Tested, B = Based on Characterization, C = By Design.
AC Electrical Specifications, RX 5TH Order LPF Individual Performance
(NOTE 13) TEST LEVEL A A A A B A B A B A A A B C
VCC = 4.5V to 5.5V
PARAMETER RX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 0 RX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 0 RX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 1 RX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 1 RX LPF Sel0, Sel1 Tuning Speed RX LPF 3dB Bandwidth Tuning LPF Tune Nominal Resistance RX LPF Voltage Gain RX LPF Single Ended Output Voltage Swing at 2k Load (Controlled By AGC Action) RX LPF Differential Input Impedance RX I/Q Channel Amplitude Match RX I/Q Channel Phase Match RX LPF Total Harmonic Distortion LPF Output Impedance, Single-Ended NOTE:
TEMP. (oC) 25 25 25 25 25 25 25 25 25 25 Full Full 25 25
MIN 1.8 3.6 7.4 14.8 -20 -1.0 4 -1 -4 -
TYP 2.20 4.40 8.80 17.60 787 0 5 3 50
MAX 2.4 4.8 9.6 19.2 1 +20 1.0 550 1 4 6 -
UNITS MHz MHz MHz MHz s % dB mVP-P k dB Degrees %
13. A = Production Tested, B = Based on Characterization, C = By Design.
4-8
HFA3761
TABLE 1. LOW PASS FILTER PROGRAMING AND TUNING INFORMATION MODE BW0 BW1 BW2 BW3 LPF SEL1 0 0 1 1 LPF SEL0 0 1 0 1 f3dB (NOMINAL RTUNE) 2.2MHz 4.4MHz 8.8MHz 17.6MHz
f 3dBNOMINAL 787 f TUNED 3dB = --------------------------------------------------R TUNE
PERCENT OF NOMINAL FREQUENCY
+20%
-20% -30 -25 -20 -15 -10 -5 0 +5 +10 +15 +20 +25 +30
[(787 - RTUNE)/RTUNE] * 100%
FREQUENCY 20% Low Nominal 20% High
RTUNE 984 787 656
FIGURE 1. TYPICAL f3dB vs RTUNE
4-9

▲Up To Search▲

Price & Availability of HFA3761

	To Download HFA3761 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .